Performance Improvement of Poly-Si Tunnel FETs by Trap Density Reduction

In this brief, the tunnel FETs (TFETs) with a polycrystalline-Si (poly-Si) channel have been demonstrated, and the performance of the poly-Si TFET shows a significant improvement by the reduction of interface trap states (N
_it
) near the conduction band edge. The ON-state current (I
_ON
) conduction mechanism, band-to-band tunneling, of poly-Si TFETs is strongly affected by the band bending of poly-Si channel. The N
₂
plasma surface treatment before the gate dielectric deposition can produce a plasma-induced interfacial layer to reduce N
_it
obviously, which greatly enhances the surface potential modulation by the gate and improves the I
_ON
value of poly-Si TFETs ~3.7×. The OFF-state current (I
_min
) attributed to the trap-assisted tunneling (TAT) can also be reduced by a factor of ~40%, because of the passivation of grain boundary trap (N
_trap
) of the poly-Si channel film. Consequently, the ON/OFF current ratio is enhanced from 9.42 × 10
⁵
to 6.13 × 10
⁶
. In addition, the subthreshold swing, I
_ON
, and I
_min
of poly-Si TFET exhibit superior short-channel effect immunity, which shows good feasibility for implementing high packing density of poly-Si thin-film transistors, such as 3-D nonvolatile memory and pixel driving device.