Thin-Film Transistor $V_{\rm th}$ Shift Model Based on Kinetics of Electron Transfer in Gate Dielectric

An analytical threshold voltage shift (ΔV
_th
) model of thin-film transistor (TFT) under gate electrical stress is presented in this paper. The model is based on the kinetics of electron transfer in the gate dielectric, namely the channel electrons first inject into the dielectric traps near the interface through trap-assisted tunneling, and then move to the traps at the further positions by Poole-Frenkel conduction. An amorphous indium-gallium-zinc oxide (a-IGZO) TFT is used as the example to verify the proposed model since its ΔV
_th
is mainly caused by the charge trapping effect. The results show that this model can provide not only a precise prediction to the ΔV
_th
of the a-IGZO TFT, but also a detailed distribution of trapped electrons in the dielectric, and thereby help with understanding the recovery of the ΔV
_th
. In addition, the dependence of the ΔV
_th
on trap density N
_T
and trap depth Φ
_t
is investigated, and the impact of the shallow oxide traps to the ΔV
_th
is therefore manifested.