High-Voltage LDMOS Transistor With Split-Gate Structure for Improved Electrical Performance

An n-channel split-gate laterally double-diffused metal-oxide-semiconductor (LDMOS) device is presented. The proposed split-gate LDMOS has a primary gate (PG) and floating gate (FG). The FG is formed by spacer etching and placed along the perimeter of the PG. The potential of the FG is determined by the potential of the PG and the capacitive coupling ratio. Therefore, the FG has lower potential than that of the PG. This potential difference along the channel length direction accelerates channel carriers, which ultimately enhances device performances. From device measurements, the fabricated splitgate LDMOS devices showed improved electrical characteristics: lower drain-induced barrier lowering; higher transconductance (g
_m
); lower drain conductance (g
_ds
= 1/
_rout
); lower ON-resistances R
_ON
; and higher early voltage V
_EA
= I
_D
/g
_ds
.