New Planar Junction Edge Termination Technique Using OPTVLD With a Buried Layer

A new planar junction edge termination technique, using the optimum variation lateral doping with a buried layer, is proposed and studied. A voltage equal to 100% of the breakdown voltage of a single-sided abrupt parallel-plane junction with the same substrate can be achieved within a smallest area on the surface. The proposed technique can be realized by a process compatible with conventional CMOS or BiCMOS technologies and verified by the results of numerical simulations.