I. Introduction
Three-Dimensional integrated circuit (3-D IC), which provides a vertical platform for multifunctional integration, has been favorably discussed and explored over the past few years as a practical approach for “More-than-Moore” technology [1]. 3-D IC provides higher density achievable without further transistor scaling by stacking several layers that are vertically interconnected. Conventionally, as technology evolves, the performance of electronic devices has become more interconnect-dominated, which results in longer global interconnects, smaller transistor dimensions, and larger chip sizes. As such, more electrical power is needed to compensate for the resistance–capacitance (RC) latency. Moreover, reliability challenges are posed on back-end-of-line (BEOL) copper/low- interconnects with reduced dimensions where electromigration (EM) significantly reduces the copper line robustness and reliability [2]. Therefore, planar circuits suffer from a significant performance loss at the interconnect-limited domain if conventional 2-D scaling is further pursued. 3-D IC can be used to partition different functional blocks into different vertical layers to reduce the total interconnect length. Consequently, lower RC delay and lower power consumption can be expected to improve the overall device performance. The common practice to realize 3-D IC is to bring all IC layers in a stack with a wide range of bonding materials. Amongst various stacking approaches, Cu–Cu bonding has attracted considerable attention as a promising bonding technique which can simultaneously form electrical, mechanical, and hermetic bonds. Compared to solder-based connections, Cu–Cu bonding provides advantages such as: 1) ultrafine pitch , which is not acheivable by current Cu/Sn bonding [3]; 2) better electrical and thermal conductivities as an interconnect medium; and 3) Cu has much better electromigration resistance [4].