Analytical Model of Center Potential in GaN Vertical Junctionless Power Fin-MOSFETs for Fast Device-Design Optimization

In this work, we present an analytical model for fast optimization of gallium nitride vertical junctionless (VJ) power Fin-MOSFET device design. The derived model faithfully captures the electrostatic behavior of the VJ Fin-MOSFET at high bias conditions. Consequently, power device operation parameter of interest such as maximum source-to-drain potential barrier (
$\phi _{\text {b,max}}$
) and its dependence on large drain bias is well-predicted. Moreover, using the derived analytical model, we show that the distance between gate and source can be tuned to improve
$\phi _{\text {b,max}}$
for countering the drain-induced barrier lowering (DIBL) effect. The analytical model derived in this work is generic in nature, and it can be adopted to optimize any ultrawide bandgap semiconductor-based VJ power Fin-MOSFET device design.