Impact of Interlayer and Ferroelectric Materials on Charge Trapping During Endurance Fatigue of FeFET With TiN/HfxZr1-xO2/Interlayer/Si (MFIS) Gate Structure

We study the impact of different interlayers (ILs) and ferroelectric materials on charge trapping during the endurance fatigue of Si ferroelectric field effect transistor (FeFET) with TiN/Hf
_x
Zr
_1-x
O
₂
/ interlayer/Si (MFIS) gate-stack. We have fabricated FeFET devices with different interlayers (SiO
₂
or SiON) and Hf
_x
Zr
_1-x
O
₂
materials (
${x} =0.75$
, 0.6, 0.5) and directly extracted the charge trapping during endurance fatigue. We find that: 1) under the same equivalent oxide thickness (EOT) condition, the increase of dielectric constant and interlayer thickness suppresses charge trapping and improves the endurance characteristics; 2) charge trapping effect is experimentally verified to be the origin of endurance fatigue; and 3) as the spontaneous polarization (
${P}_{\text {s}}{)}$
of the Hf
_x
Zr
_1-x
O
₂
decreases from
$25.9~ \boldsymbol {\mu } \text{C}$
/cm
²
(Hf
_0.5
Zr
_0.5
O
₂
) to
$20.3~ \boldsymbol {\mu } \text{C}$
/cm
²
(Hf
_0.6
Zr
_0.4
O
₂
), the charge trapping behavior decreases, resulting in the slow degradation rate of memory window (MW) during program/erase cycling; in addition, when
${P}_{\text {s}}$
further decreases to
$8.1~ \boldsymbol {\mu }\text{C}$
/cm
²
(Hf
_0.75
Zr
_0.25
O
₂
), the initial MW nearly disappears (only ~0.02 V). Thus, the reduction of
${P}_{\text {s}}$
could improve endurance characteristics. On the contrary, it can also reduce the MW. Our work helps design the MFIS gate-stack to improve endurance characteristics.