Strained Silicon-on-Insulator Platform for Cointegration of Logic and RF—Part I: Implant-Induced Strain Relaxation

The relaxation of tensile strain in fully depleted (FD) strained silicon-on-insulator (SSOI) by means of ion implantation is experimentally demonstrated in this work. This could enable SiGe p-channel field-effect transistors (pFETs) with high compressive strain (after ion implantation and Ge condensation) to be formed together with Si n-channel field-effect transistors (nFETs) with high tensile strain on the same substrate. From simulations in advanced technology node, 0.8% strain of nFETs and -0.9% strain of pFETs in fin structures can provide saturation drain current and peak G
_m
enhancements of ~20%-30%. f
_T
and f
_max
benefit greatly from strain across the entire range of V
_G
, with their peak values increasing significantly, thus allowing SSOI devices to meet 5G targets. In addition, forward back-bias shifts f
_T
and f
_max
curves toward lower | V
_G
|, enabling reduced power consumption at the same high performance and providing better linearity. Hence, the ability to form highly strained nFETs and pFETs together on a common FD-SSOI substrate paves the way for it to become the ultimate high-performance complementary metal-oxide-semiconductor (CMOS) platform for 5G RF and logic circuits. The relaxation of the tensile strain is demonstrated and documented in Part I. A novel Comb-like device architecture to further enhance the SSOI electrical and RF performance is provided in Part II.