Impact of Source-to-Gate and Drain-to-Gate Overlap Lengths on Performance of Inverted Staggered a-IGZO TFTs With an Etch Stopper

We report a comprehensive study on the impact of source-to-gate (LS) and drain-to-gate (LD) overlap lengths on the performance of amorphous indium-gallium- zinc-oxide (a-IGZO) thin-film transistors (TFTs) employing the inverted staggered structure with an etch stopper (ES). Although drain current (ID) is found to marginally decrease with increasing LS, it is found to considerably increase with LD. With the help of technology computer-aided design (TCAD) simulations, the increase in ID with LD is attributed to backchannel formation in the region beneath the drain, while the decrease in ID with increasing LS is attributed to the depletion of carriers from the backchannel in the region beneath the source. In addition, the threshold voltage (VTH) shifts negatively with increasing LD and drain voltage(VD). All these effects are more pronounced in short channel TFTs than long channel TFTs, which could be the origin of the anomalous dependence of VTH of the ES-type a-IGZO TFTs on channel length.