Memory-Logic Hybrid Gate With 3-D Stackable Complementary Latches

In this article, a single-layer complementary latch (CL) and one multilayer CL which are fully compatible with standard FinFET CMOS processes are characterized and their applications are extensively discussed. Through the complementary pair with the 3-D stackable twin-bit resistive random-access memory (RRAM) which consists of a TaON-based resistive film, the CLs feature great area efficiency and stable output responses. By measurement, the characteristics of the 3-D stackable twin-bit RRAM are discussed. Besides, the power, output voltage distribution, and data restoration time of the CLs are analyzed and compared.