Computing-in-Memory Architecture Using Energy-Efficient Multilevel Voltage-Controlled Spin-Orbit Torque Device

Conventional von Neumann architecture suffers from data trafficking and power hungriness between memory and processing units. Recent architectures escalating to overcome these limitations are near-memory architecture (NMA) and computing-in-memory (CiM) architecture (CMA). Spintronics-based devices, such as spin-transfer torque magnetic memory (STTM), spin-orbit torque magnetic memory (SOTM), differential spin Hall-effect-based magnetic memory (DSHEM), and multilevel voltage-controlled SOT-based magnetic memory (MV-SOTM) are a few promising contenders for post-CMOS technology. MV-SOTM spin device is used in this study to showcase the CMA to perform basic logic operations namely AND/ NAND, OR/ NOR, and XOR/ XNOR within the memory array. Furthermore, magnetic full adder (MFA) is implemented using CMA in MV-SOTM array. The performance of CMA design for MV-SOTM-based MFA is compared with SOTM-based MFA. The proposed CiM design for MV-SOTM-based MFA shows 29.2% and 12.22% performance improvement in terms of write energy and logic power, respectively. Moreover, up to 34% area reduction is achieved in comparison to SOTM-based CiM MFA.