Trap Passivation for Reducing On-Resistance and Saturation Voltage in Wafer-Bonded InGaAs-Channel/GaN-Drain Vertical FETs

High frequency and high power are the driving forces behind semiconductor transistor technology. However, conventional devices have the tradeoff of either being high speed or high breakdown—but not both. Wafer-bonded current aperture vertical electron transistors (BAVETs) help eliminate the tradeoff by combining a high-speed III-As channel to a high-breakdown III-N drift region. The device presented herein comprises of an InAlAs gate-barrier/InGaAs channel, wafer-bonded to an InGaN/GaN drift region, with the InGaAs/InGaN interface referred to as the wafer-bonded interface (WBI). The electronic behavior of WBIs is yet less known but necessary in realizing the potential of a BAVET. Herein, strong trap activity at the WBI is shown to be the cause of abnormally high saturation voltage (
${V}_{\text {DS}\_{}\text {SAT}}$
) in BAVETs. The traps cause unintentional space charge (SC) region in the drain region of the device. This causes a drain resistance, a higher ON-resistance (
${R} _{\text {ON}}$
), and a higher
${V}_{\text {DS}\_{}\text {SAT}}$
. The challenge is overcome by hydrogen passivation of traps at WBI by using a p-doping for the InAlAs layer, which reduces the trap-charge concentration at the WBI. Consequently, the width of the SC region is reduced and a reduction in
${V}_{\text {DS}\_{}\text {SAT}}$
is demonstrated, wherein it reduces from >12 to 5 V.