On-Chip Characterization of Ultra-Low Voltage Standard Cell Library Considering Input Slew and Output Capacitance

The propagation delay of a logic gate in a standard cell library (SCL) primarily depends on the input transition time (slew) and output load capacitance. In this article, we proposed an area-efficient test structure, which can measure the delay of the logic gate considering input slew and output load conditions at ultra-low voltage. The proposed circuit consists of a reconfigurable ring oscillator (RRO), which can configure the input slew and output load of each logic gate in the ring oscillator (RO) during the delay measurement. A test chip has been fabricated in an industrial
$130 {n}\text{m}$
process node to validate the proposed concept. Within-die and die-to-die variations of gate delay across different slew and load conditions are studied and analyzed for sub-threshold regions of operation. Ten chips are tested and measured across supply voltages with output loads and input slew conditions. The measured results agree with the simulation results.