Degradation Evaluation and Defects Analysis for 1.2-kV Planar-Gate SiC MOSFETs Under Repetitive Surge Current Stress

In this work, we have comprehensively investigated the degradation behaviors and mechanism of 1.2 kV silicon carbide (SiC) metal oxide semiconductor field-effect transistors (MOSFETs) under repetitive surge current stress. The experimental results show that the negative drift of threshold voltage (
${V}_{\text {th}}$
) is related to the gate turn-off voltage and the surge current. The gate leakage current (
${I}_{\text {gss}}$
) increases by about one order of magnitude after the stress. The deterioration of the electrical parameters is considered to be the gate oxide degradation associated with the increase of SiC/SiO2 interface traps. By using the low-frequency noise (LFN) technique, it is demonstrated that the trap density of the device with the most severe degradation after the stress becomes 3.5 times the initial one. On the other hand, we observed that the voltage drop (
${V}_{\text {sd}}$
) of the body diode and on-resistance (
${R}_{\text {ds}(\mathrm{\scriptscriptstyle ON})}$
) increased. It is attributed to the cumulative degradation process of package with the appearance of fatigue in the bond wire induced by the thermo-mechanical stress during the surge test. This work can serve as a valuable reference for the reliability of SiC MOSFETs.