Process Yield and Device Stability in Sol-Gel Alumina Passivation Layer-Based GFETs

The stability of graphene FET (GFET) devices is a significant problem and needs a good passivation layer to protect from ambient-based degradation. Low-cost and low-temperature sol-gel alumina passivation layer-based GFETs are studied here with the goal not only to improve the stability of the GFET device but also to achieve high process yield. The process yield and device stability are explored for two different molarities (0.1 and 0.05 M) of sol-gel Alumina. The blanket film study [ellipsometry and X-ray photoelectron spectroscopy (XPS)] and transistor studies (optical and electrical characterizations) were carried out to compare the two sol-gel Alumina molarities in terms of process yield and device Stability and hence identify the most suitable sol-gel Alumina molarities. The results indicate that 0.1 M sol-gel Alumina deposited GFETs have problems: 1) process yield due to crack formation in the channel region post-annealing, where close to half of the devices are working; and 2) working devices are not stable and degrading very fast within a week’s time. This degradation can be attributed due to insufficient solvent removal and higher concentration of oxygen vacancies present. On the other hand, the 0.05 M sol-gel Alumina-based GFETs exhibit 100% process yield with all working devices and stable behavior for more than two months. Hence, this work proposes an optimized process recipe for a sol-gel Alumina-based passivation layer to achieve the best possible process yield and device stability for GFETs.