Enhancement of Silicon Critical Breakdown Field by Reducing the Avalanche Breakdown Distance to Improve the Breakdown Voltage of Thin SOI Device

This article presents an analytical model for a thin silicon-on-insulator (SOI) device based on the enhancement of silicon critical breakdown field technology. Solving the 2-D Poisson equation in the thin drift region reasonably explains the physical mechanism that the thin silicon layer enhances the critical breakdown field of silicon material. Meanwhile, a new ultrathin SOI lateral double diffused metal oxide semiconductor field effect transistor with electron accumulation layer is proposed, named EA SOI LDMOS, to verify the proposed model and improve the tradeoff between breakdown voltage (BV) and specific ON-resistance (
${R}_{\text {on,sp}}{)}$
. The electron accumulation provides a new conduction path under the gate oxide layer, resulting in a lower resistance compared with conventional thin SOI LDMOS. The various thickness of the thin silicon layer enhances the critical breakdown field of silicon, which increases the BV of EA SOI LDMOS. The results show that the
${R}_{\text {on,sp}}$
of EA SOI LDMOS is decreased from 303
$\text{m}\Omega \cdot $
cm2 of the conventional ultrathin SOI LDMOS to 207
$\text{m}\Omega \cdot $
cm2, which is 32% lower with the same BV. The analytical results of the electrical characteristics are in good agreement with the results from numerical simulations.