High Voltage PDMOS Device Design Against Breakdown Voltage Walk-In

This article studies the design strategy to build operating and manufacturing robustness into a metal and polysilicon field plate-assisted Reduced Surface Field Effect (RESURF)
$\vert 225 \text{V}\vert $
P-type double diffuse metal oxide silicon (PDMOS) device against Breakdown Voltage Walk-In. The article uses technology computer-aided design (TCAD) to calibrate the unique walk-in properties of charge trapping along the thermal oxide interface of the extended drift region with a trap density of
$7{e}^{{11}}$
eV
$^{-{1}}$
cm
$^{-{2}}$
, a trap occupancy breakdown voltage temperature coefficient of 1.9 V/K, and a breakdown voltage walk-in plateau of −133 V determined by the opposing electric field from the fully occupied traps inhibiting the resurf mechanism. Using this calibration, the article goes on to solve the walk-in mechanism by using a junction resurf field plate buried in the silicon lattice to create an electric field from the depleted dopant that balances the effects of the oxide-trapped charges. The design of the buried resurf field plate is optimized with TCAD for a robust
$\vert 225 \text{V}\vert $
operating voltage. This robustness is confirmed with measured silicon data.