Modeling Study of Power-On and Power-Off System-Level Electrostatic Discharge Protection

System efficient electrostatic discharge (ESD) design is an effective method for simulating the ESD behaviors of a system. Based on this simulation method, this article mainly investigates the transient behaviors of a system-level ESD protection circuit with and without a 2.5 V power supply. During power-
on
state, latch-up levels of a feedback power clamp protected by off-chip elements are predicted and mainly analyzed under machine model stress. During power-
off
state, the physical failure of a hybrid-triggered power clamp under surge stress is investigated. In addition to the utilization of transmission line pulsing (TLP)
I-V
curves, transient TLP waveforms are also used for building the component models in the system-level ESD protection circuit. Moreover, the relevant measurements for the power-
on
state and power-
off
state are included in this article for verifying the simulation results. For ESD designers, this article provides a complete modeling and analysis process of co-design protection circuit to investigate the electrical behaviors.