I. Introduction
Increasing interconnect circuitry density and shrinking product form factor are the current trends in high-speed electronic device design [1]. As a result, printed circuit board (PCB) traces are closely routed to each other. It is quite common that the traces on adjacent layers of the PCB could intersect [2], [3]. For high-speed designs, electromagnetic interference issues (such as crosstalk) could significantly affect their electrical performance [4]. Thus, it is critical to estimate the crosstalk between two intersecting traces on adjacent layers of a PCB during the early PCB design stages. This way, the potential risk of signal integrity and EMI problems can be reduced.