I. Introduction
Wireline communication devices are susceptible to electromagnetic interference (EMI) generated by other integrated circuits (ICs). Previous works in [1], [2], and [3] provide detailed analyzes of postfabrication circuit failures that occur due to EMI. Traditional EMI suppression methods use EMI shields and passive filters [4], [5], [6]. However, these methods increase the bill of materials, the volume, and the total turnaround time of the product. Therefore, entirely on-chip solutions for EMI suppression are very attractive in space-constrained electronic devices despite the marginal increment that is required in the silicon area. The work in [7] proposed a simple method to model and emulate the effect of EMI, and incorporate them into the SPICE simulations to analyse the impact of the EMI on the circuits.