Predictive Modeling for Estimating the Limits for Nonpersistent Effects in MOSFET Response Under Large Signal Gate Injection

In this article, we focus on developing predictive upset models to characterize the nonpersistent effects of large-signal gate-side injection on n-type and p-type metal-oxide semiconductor field-effect transistors (mosfets). By “nonpersistent,” we refer to a set of conditions that do not affect the physical characteristics of the device or exhibit any memory effects, i.e., the device will operate normally once the injected large signal stimulus is removed. We present predictive models that determine the maximum limits for large-signal gate-side injection in terms of the device's ION/IOFF ratio prior to degradation or damage to the device. A function based on the mosfet technology device parameters, such as its threshold voltage and its power supply rating, is developed and presented. We then validate our predictive models against experimentally measured data for complementary metal-oxide-semiconductor (CMOS) mosfet devices fabricated using 350, 180, 130, and 65 nm standard Taiwan Semiconductor Manufacturing Company (TSMC) CMOS processes. Based on our validated predictive models, we show how the maximum limits for large-signal gate-side injection at 10-MHz change with technology scaling, from ~9.7 dBm for 350 nm to ~-1.7 dBm for 65-nm technology nodes for n-type mosfets; and, from ~11.0 dBm for 350 nm down to ~1.2 dBm for 65-nm technology nodes for p-type mosfets. We anticipate that our predictive models can be leveraged by CMOS circuit designers and electromagnetic interference/compatibility (EMI/EMC) engineers as quick “rule of thumb” guidelines to estimate device and circuit level susceptibility for the injected large signals.