High-Frequency Electromagnetic Eddy Effect Modeling for Cylindrical and Tapered Bump

In recent 3-D integrated circuits, tapered-shaped bumps (
T
-bump) have provided an appealing solution over the conventional cylindrical (
C
-bump) structures due to their reduced parasitic and area requirement. At high frequencies, the nonuniform current distribution and electromagnetic (EM) field produce the eddy effect that primarily affects the through silicon via (TSV) bump performance in the 3-D packaging system. In this regard, this article presents the first realistic and holistic method to analyze the impact of eddy currents on the
T-
and
C
-bump. Furthermore, a novel resistance–inductance–conductance–capacitance model is proposed to incorporate the effects of bump, intermetal dielectric, and eddy currents. An analytical solution for the
C
- and
T
-bump is proposed using the principles of the partial inductance, Maxwell equations, and differential scalar potential. In order to benchmark, the quantitative values of TSV-bump parasitics are validated against the experimental and structural EM simulations. Encouragingly, good agreement with an average deviation of only 3.1% has been observed. Using a driver via load at 7-nm technology, the crosstalk-induced delay, peak noise voltage, power dissipation, insertion (
S
21), and reflection (
S
11) losses are analyzed with and without considering the eddy impact. The performance parameters are further validated with the analytical finite-difference time-domain approach. It is worth emphasizing that the
T
-bump significantly reduces power dissipation, crosstalk, peak noise, insertion, and reflection losses when compared with the
C
-bump counterparts. The overall percentage deviation while incorporating the eddy effect is approximately 11.78%, 10.18%, 17.17%, 26.70%, and 45.08% for the crosstalk, peak noise, power dissipation, insertion, and reflection losses, respectively.