Contents 1 Introduction
To prevent reverse engineering and design plagiarism, much research has been done recently on hardware obfuscation. It is an intellectual property (IP) protection technique that modifies the original circuit to conceal the functionality. Even if the netlist is recovered and copies of the circuits are made, they do not function correctly without proper keys. Most existing hardware obfuscation techniques are at the gate or layout levels. They usually encrypt the circuit by introducing additional keyed gates or obfuscating states [1], [2], [3], [4]. Unfortunately, inserting keyed gates may increase the critical path and these techniques are still subject to state-of-the-art reverse engineering methods, especially satisfiability (SAT) based attacks [5], [6]. Although several approaches attempted to counter SAT attacks in the literature [4], [7], [8], recent studies have shown that these defenses can still be compromised by more advanced SAT-based attacks [9], [10].
