A Single and Adjacent Error Correction Code for Fast Decoding of Critical Bits

Many systems have critical bits which must be decoded at high speeds; for example, flags to mark the start and end of a packet (SOP and EOP) determine subsequent actions, thus they must be decoded first and fast. This paper presents a new single and adjacent error correction (SAEC) code; as the codewords have critical bits, the proposed code accomplishes a fast decoding for them. The proposed code is a systematic code and permits shortening. This is accomplished by reducing the information bits, so that columns in the H matrix can be eliminated, while still keeping both the SAEC capability and the systematic feature, but for an odd number of information bits, an adjustment step in critical bits is required. It is shown that the check bit length of the proposed code is nearly the same as that of the traditional (optimal) Hamming SAEC code. The decoder of the proposed SAEC code is compared with the traditional Hamming SAEC code; this comparison shows that on average, the delay time for the critical bits is reduced by 6 percent compared with the traditional Hamming SAEC code (so at the same reduction level as a previous SEC scheme for fast decoding of critical bits over a traditional SEC code). Also, the area and power consumption of the proposed decoder show average reductions of 12 percent and 10 percent compared with the decoder of a traditional SAEC code.

1 Introduction

Error control codes (also referred to as error correcting codes, ECCs) are widely used to improve system dependability, in particular for communication and storage systems [1]. Based on application and requirements, high speed ECC decoding is often required and usually implemented using a parallel decoding scheme. Parallel decoding does not use feedback shift registers because it must execute in only few clock cycles. Several parallel decoding schemes have been proposed [1], [2]; some of these schemes target burst ECCs [1], [3], [4]. The scheme of [5] considers long codewords; some codes suitable for parallel decoding, e.g., orthogonal Latin square codes, have been studied [6] and few schemes have been analyzed to reduce the delay of a parallel decoder [7], [8].