An Area-Efficient In-Memory Implementation Method of Arbitrary Boolean Function Based on SRAM Array

In-memory computing is an emerging computing paradigm to breakthrough the von-Neumann bottleneck. The SRAM based in-memory computing (SRAM-IMC) attracts great concerns from industries and academia, because the SRAM is technology compatible with the widely-used MOS devices. The digital SRAM-IMC scheme has advantages on stability and accuracy of computing results, compared with the analog SRAM-IMC schemes. However, few logic operations can be implemented by the current digital SRAM-IMC architectures. Designers have to insert some special logic modules to facilitate the complex computation. To address this issue, this work proposes an area-efficient implementation method of arbitrary Boolean function in SRAM array. Firstly, a two-input SRAM LUT is designed to realize the arbitrary two-input Boolean functions. Then, the logic merging and the spatial merging techniques are proposed to reduce the area consumption of the SRAM-IMC scheme. Finally, the SOP-based SRAM-IMC architecture is proposed, and the merged SOPs are mapped into and computed in it. The evaluation results on LGsynth’91, IWLS’93 and EPFL benchmarks show that, the area of the synthesis results based on the ABC tool is 3.69, 5.72 and 1.86 times of the circuit area from the proposed SRAM-IMC scheme in average respectively. Furthermore, the circuit area from the original SOP-based SRAM-IMC scheme is 2.07, 1.99 and 1.86 times in average of the circuit area from the proposed SRAM-IMC scheme respectively. The performance evaluation results show that the cycle consumption of the proposed SRAM-IMC scheme is independent to the scale of the input Boolean functions.

I. Introduction

The artificial intelligence (AI) and big data applications boost in recent years, which results in the tremendous demands of computing power. Till now, the von-Neumann architecture is the prevailing architecture of the general-purpose computing platforms, in which the memory banks and the processor cores are separated. The frequent data transfers between the memory and the processor cores decline the computation efficiency and increase the energy consumption, due to the limited bandwidth of the data exchange channel. It is aggravated when the data-intensive tasks are performed. The in-memory computing (IMC) is proposed as an emerging computing paradigm to address the challenge of the von-Neumann bottleneck. The hardware platform based on resistive random access memory (RRAM), phase change memory (PCRAM) and other kinds of non-volatile memories are broadly used in the IMC research. M. R. H. Rashed et al. proposed RRAM-based digital and hybrid analog-digital IMC architectures [1], [2], [3]. And Wang et al. [4] and Thijssen et al. [5], [6] further proposed the logic synthesis methods for the RRAM-based digital and hybrid IMC. Nevertheless, comparing with the emerging non-volatile memories, the static random access memory (SRAM) has advantages on data endurance, yield and process maturity. It also has faster access speed and the better process compatibility with CMOS technology, compared with the dynamic random access memory (DRAM) and the Flash memory. As a result, the SRAM-based IMC (SRAM-IMC) architecture is of great concern from academia and industries in recent years.