Traffic Characterization Based Stochastic Modelling of Network-on-Chip

The trend towards multi-core and many-core processors has changed the landscape of computers and servers. Now the performance of a microprocessor heavily depends not only on the data path but also on the memory technology and communication technology. On-chip communication networks or Network-on-Chip is a component which facilitates communication between the cores of a microprocessor. In this manuscript we propose an analytical model for the analysis of Network-on-Chip performance based on Jackson queuing networks for applications that exhibit Poisson injection process. The injection process statistics and the traffic profile of PARSEC benchmarks have been characterized. We have shown that injection process of PARSEC benchmarks does not match with the well known probability distributions using Quantile-Quantile plot and Kolmogorov-Smirnov test. For realistic benchmarks that does not follow Poisson injection process we propose
$G/D/1$
queuing model for the NoC router. We have carried out performance analysis using the traffic characterization in conjunction with our analytical model for prediction of performance metrics. The analytical model offers a speed up of around 13 times in comparison with the simulation based performance evaluation. The percentage of error between the analytical model and simulation is less than 6% for most of the benchmarks except Canneal and Ferret. We have also compared our analytical model results with the results of SNIPER simulator.