Python Subset to Digital Logic Dataflow Compiler for Robots and IoT

Robots and IoT devices must process real-time signals using embedded systems with limited power and clock speeds – rather than large CPUs or GPUs. FPGAs offer highly parallel computation, but are difficult to program, both algorithmically and at hardware implementation level. Programmers of digital signal processing (DSP), machine vision, and neural networks typically work in high level, serial languages such as Python, so would benefit from a tool to automatically convert this code to run on FPGA. We present a design for a compiler from a serial Python subset to parallel dataflow FPGA, in which the physical connectivity and dataflow of the digital logic mirrors the logical dataflow of the programs. The subset removes some imperative features from Python and focuses on Python’s functional programming elements, which can be more easily compiled into physical digital logic implementations of dataflows. Some imperative features are retained but interpreted under alternative functional semantics, making them easier to parallelize. These dataflows can then be pipelined for efficient continuous real-time data processing. An open-source partial implementation is provided together with a compilable simple neuron program.