Standard Cell Library Characterization Flow Using Open Source Tools with Google + SkyWater 130nm PDK

This paper presents a comprehensive library characterization flow aiming to streamline and enhance the efficiency of digital circuit design procedure using open source tools. The flow incorporates an open source layout design tool, to create circuit layouts, with subsequent SPICE netlist extraction to obtain precise description of the circuit including active devices and parasitic RC components. The flow employs an open source SPICE simulator, leading to the generation of a comprehensive Liberty (.lib) file. Additionally, the flow includes the creation of a Library Exchange Format (.lef) to facilitate seamless integration with Automatic Place and Route (P&R) tools. This innovative approach contributes to the open source ecosystem, providing a valuable resource for designers working with the open source technology. The library characterization flow is used to characterize open source Google + SkyWater 130nm technology. The results demonstrate the effectiveness of the proposed library characterization flow, offering a reliable and a scalable foundation for digital circuit designers using the open source PDK. This research contributes advancing the capabilities of open source design methodologies, fostering collaboration and innovation in the field of integrated circuit design.

I. Introduction

The evolution of CMOS transistor fabrication has brought about significant alterations in the configuration and arrangement of standard cells, thereby enhancing the performance and precision of VLSI circuits. The contemporary design landscape in advanced technology relies on the support of both fabrication and commercial entities. To safeguard against potential technology leaks, stringent measures are implemented by both fabrication companies and commercial EDA vendors to protect the proprietary design environment.