An 87.25 dB Open-Loop Gain, 2.09 GHz Unity Gain Bandwidth 3-Stage Operational Amplifier Implemented Using 45nm Technology

A three-stage operational amplifier (op-amp) designed and analyzed in depth using the Cadence design environment is presented in this work. The suggested op-amp design consists of three separate stages: a differential amplifying stage, an output transconductance stage (OTS), and a gain boosting (or buffer) stage. It is implemented using 45 nm CMOS technology in the Cadence Virtuoso environment and powered by ±0.9 V rails. With the least amount of power consumption possible, this design seeks to provide high gain, wide bandwidth, and stability. With a gain of87.25 dB, the total power dissipation is measured at 21.85 mW. A phase margin of 60.57 degrees and a unity gain bandwidth of 2.09 GHz are shown by the simulation results, suggesting outstanding stability throughout the frequency spectrum. The layout of the proposed op-amp occupies 3832.452 μm ^2 with clean Design Rule Check (DRC) and Layout versus Schematic (L VS) results. DC analysis maintains a current of 5.11374 nm, while the slew rate is measured at 0.2079 V /μs. Additionally, simulations for Power Supply Rejection Ratio (PSRR) and Common Mode Rejection Ratio (CMRR) are performed and validated in this study.