A Study of the Effects of Thermal Budget on 3D-NAND Charge Trap Cell Reliability

In this paper, we present the advantages of using a CMOS wafer bonded to a cell array wafer by advanced interconnect, which shows a significant 3D-NAND memory window (MW) improvement. This paper discusses the physics with the cell reliability dependence on the thermal budget and the associated process optimizations needed to mitigate the adverse effects. The cell array wafer stacking with a CMOS wafer approach is a key enabler for future 3D-NAND scaling roadmap.