Hot-Carrier-Induced Degradations and Optimizations for Lateral DMOS Transistor with Shallow Trench Isolation and Step Oxide Improvement

In this paper, hot carrier injection degradation in 80 V NLDMOS with shallow trench isolation (STI) is investigated and improved through STI corner rounding and thick STI oxide, step oxide and gate oxide optimization.
$\Delta \text{Idlin}$
has different behavior with stress time at different conditions of Vgs (Isubmax and Vgmax). Combined with TCAD (Technology Computer Aided Design) simulation and experimental data, degradation mechanism was revealed. When the device is stressed under Vg (Isubmax), the hot electrons in the proximity of the accumulation region and source-side STI corner is the main cause of strong HCI degradation effects. For the device stressed under high Vgs (Vgmax), at first, drainside STI interface degradation by hot electrons is the major cause. Then with the increasing stress time, the drainside corner trap hot electrons and source-side STI oxide and step oxide trap hot holes, ultimately leading to
$\Delta \text{Idlin}$
almost unchanged. Finally, only the hot electrons of drainside STI corner and drift region played a predominant role, resulting in that
$\Delta \text{Idlin}$
revert to initial slope. Fortunately, it is concluded that STI corner rounding and thick STI oxide, step oxide and gate oxide are novel and effective method to optimize the HCI reliability according to combining with TCAD and experimental data.