Mirroring ATPG Technology for Multi-Core Chips

Multi-core multiplexing scenarios are common in today's ultra-large-scale network system chips and large computing power chips such as CPUs and GPUs. To screen out chips with manufacturing defects and to improve product quality, the traditional automatic test pattern generation(ATPG) method requires large numbers of input and output(I/O) pins. In this paper, a novel idea called Mirroring ATPG is proposed to reduce the I/O resources and improve the efficiency of ATPG test.