Preemptive FPGA Scheduling Based on Dynamic Partial Reconfiguration

With the increasing scaling of computation workloads, heterogenous computing systems including different kinds of computing platforms such CPU, GPU or FPGA become increasingly important. To exploit the parallelism of FPGA within a heterogenous system, dynamic partial reconfiguration is a powerful technique to enable the FPGA dynamically changes its workload in execution, and hence implement a scheduler which can schedule more tasks to meet their deadlines.