A 106TOPS/W SRAM Compute-in-Memory Macro in 28NM With Reconfigurable Bitwise Operation for AI

This paper proposes a 64kb SRAM-based full-precision reconfigurable Compute-In-Memory (CIM) architecture in a 28nm technology. Both MAC and basic Boolean operation units are integrated within the CIM macro, which allows the system to adapt to different computational tasks. The Adder tree, a critical building block in CIM, is optimized by utilizing a simplified 14-T based full adder. This optimization leads to improvements in energy efficiency and savings in area. The simulation results demonstrate the performance of the proposed CIM macro, achieving a 106 TOPS/W energy efficiency at a 0.9V power supply. The total area is around 0.5mm
²
.