A Comprehensive Study of Read-After-Write-Delay for Ferroelectric VNAND

Read-After-Write-Delay (RAWD) is an important show-stopper (S.S) in ferroelectric based VNAND (Fe-VNAND) because the read speed is fundamentally limited by neutralization time of trapped charges between the ferroelectric layer and the interfacial oxide layer. We investigated the RAWD time (t
RAWD
) in Metal-Ferro-Insulator-Silicon (MFIS) gate stack and extended the analysis to Laminate-MFIS (LaMFIS), which are candidate for achieving higher memory window (M.W) in Fe-VNAND. After applying a positive voltage to MFIS and LaMFIS, it was confirmed that it takes about ‘1 second’ for the normal state, low threshold voltage (LVT), which is caused by excessively injected electrons from the channel. What is unusual in LaMFIS is that V
t
decreases further after about '10 seconds', which is caused by electrons deeply trapped in the inserted layer between the ferroelectric layers. In LaMFIS, there is a phenomenon in which V
t
rises slightly at low voltage of Incremental Step Positive Pulse (ISPP) operation. This is related to accumulation of deeply trapped electrons. The newly devised novel ISPP successfully removed these electrons and improve device speed and ISPP variation. Lastly, the RAWD of Metal-Insulator-Ferro-Insulator-Silicon (MIFIS) gate stacks, another candidate for achieving high M.W was analyzed.