Scaling Trends and Bias Dependence of SRAM SER from 16-nm to 3-nm FinFET

SRAM SER measurements show a decrease in per-bit susceptibility at the 3-nm FinFET node compared to the 5-nm FinFET node, contrary to the trend observed between the 7-nm and 5-nm FinFET nodes. Robust data across various supply voltages demonstrate a pronounced exponential bias influence on 3-nm FinFET SRAM SER, distinguishing it from earlier FinFET processes. Simulation and modeling attribute these trends to variations in
$Q_{crit}$
and
$Q_{coll}$
. These findings highlight that SER scaling trends in advanced FinFET processes do not necessarily align with the standard scaling trends observed in prior nodes.