Missing Trigger Circuit Action and Device Engineering for Conventional Nanoscale SCR

In this work co-optimization of silicon-controlled rectifier (SCR) ESD characteristics with its low voltage trigger circuit is presented. Resistance and Capacitance (RC) controlled thick gate NMOS and PMOS based circuits have been explored and compared. The design approach is discussed and presented for low trigger SCR for two different trigger circuits. In the process we find that some of the trigger circuits previously reported in literature do not work as desired until co-optimized device engineering techniques are used. The circuit insights are explored using well calibrated electrothermal 3D process and device TCAD mixed mode simulations.