Understanding the Physical Mechanism of RowPress at the Device-Level in Sub-20 nm DRAM

In this work, we investigated the RowPress (RP) effect at the device-level for sub-20 nm DRAM. Utilizing 3D TCAD simulations, single-and double-sided RP are studied and compared with row hammer (RH) results. The distinct leakage mechanisms of RP are identified, illuminating its different cell vulnerability in contrast to RH. AWL-induced RP results in “0” failure, whereas PWL-induced RP leads to “1” failure, demonstrating different bit-flip directionality from RH. Furthermore, differences in the dependences on temperature and access pattern between RH and RP are highlighted, and the underlying mechanisms are analyzed.

I. Introduction

Recently, RowPress (RP) has been systematically investigated through chip-level experimental characterization as a circuit-level crosstalk problem in advanced DRAM [1], emerging as a new reliability and security concern besides the widely-discussed row hammer (RH) effect [2]–[5]. Although the primary difference between RH and RP tests is the extended aggressor WL activation time (tAggON) for RP characterization, RP can significantly reduce the activation count threshold (NAC) by several orders of magnitude and behaves differently from RH in many aspects [1], indicating its different failure mechanism. However, the underlying physical mechanisms of RP are still not fully understood to date, a crucial gap in knowledge for analyzing RP features and developing efficient mitigation techniques.