A 470μW 20kHz-BW 107.3dB-SNDR Nested CT DSM Employing Negative-R-Based Cross-RC Filter and Weighted Multi-Threshold MSB-Pass Quantizer

Many loT applications require high-resolution delta-sigma modulator (DSM) ADCs with good power efficiency. To meet this demand, one current technical trend involves employing a continuous-time (CT) topology as opposed to a switched-capacitor topology since the CT topology offers easy-driven and anti-aliasing features. Nevertheless, kHz-level-BW CT DSM often requires MΩ-range high-R resistors [1]–[3]. Using normal poly resistors to implement the MΩ-range resistors consumes large silicon area and introduces large distributed-parameter parasitic capacitance. It induces a large PVT-sensitive loop delay, which deteriorates the loop transfer function. This can be overcome by utilizing high-R poly resistors offered by some special processes, which, however, are not often available. Using improved DSM architectures is the other technical trend towards achieving high resolution with good power efficiency. An emerging architecture in this field is the nested DSM. It offers a favorable balance between power efficiency and linearity by separating the processing of the MSB and the LSB. However, the long loop delay of the MSB-pass loop constrains its usage to signal bandwidths below 10kHz [4]. This paper proposes a nested CT DSM, employing a negative-R-based cross-RC filter and a weighted multi-threshold MSB-pass quantization scheme to address the above two challenges.