Design of Latch Implemented by Cellular Neural Networks

Cellular neural network is a structural form, and this article implements the design of a latch based on cellular neural network. The latch consists of eight misaligned soft error tolerance units (ST) and four input clock controlled C units. The ST unit is designed with transistor stacking based on the voltage reversal polarity of transient pulses, which enables it to have blocking characteristics while reducing the number of sensitive nodes and reducing area overhead. By utilizing clock control technology and high-speed transmission paths, latency has been significantly reduced. Under the 22 nm CMOS process, HSPICE simulation shows that compared to quadruple node upset reinforced latches (QNUTL, LSQNUSR, 4NUHL), the average delay of the latch is reduced by 38.63%, the average power consumption is increased by 58.84%, the average area overhead is reduced by 22.84%, the average power consumption delay product is reduced by 3.77%, and the average area power consumption delay product is reduced by 25.68%. Variation analysis shows that the delay of the latch is not sensitive to voltage and temperature variation. Therefore, com-pared to the existing reinforced latch design, the delay, PDP, and APDP of this latch have significantly improved.