RTL Simulation Acceleration with Machine Learning Models

Simulation-based verification of register transfer level (RTL) designs is a time-consuming process that can delay the time to market for new products. This work explores the use of machine learning (ML) to speed up RTL simulation. The authors first show that accurate ML models can be trained for common RTL modules, such as full adders, shift registers, arbiters, data transfer protocol, and parity checkers, using a small amount of data. We then present two case studies to demonstrate the applicability of our proposed ML models in RTL verification. The experimental results show that ML can be a promising technique for speeding up RTL simulation. To the best of our knowledge, this is the first work that applies ML to speed up RTL simulation.