Analysis of CMOS Full Adder Circuits for Multiplier Logic Architectures

High efficient digital adder logic circuits are very essential and critical modules in the processor and controller architectures. For example, an adder circuit in an arithmetic logic unit circuit must offer high speed operation and low power per calculation to make it an optimized processor. Apart from this, adder logic is also used to carry out subtract operations, multiply and division operations. Logic circuits such as Full adders and multipliers have become very elementary components of signal processing operations. Full adder logic circuits are implemented by using different technologies such as conventional complementary metal oxide semiconductor transistors, transmission gate logic, using different transistor counts, gate diffusion input adder and pass transistor logic based circuits. Improvements and scaling in integrated circuit design technologies have led to the circuits to operate at less critical path delay, less power consumption and final less values of power delay product. In this work, two full adder logics are simulated at 0.09 micrometer CMOS process technology in analog design environment of cadence tools. The simulation results shows that the pass transistor logic offers a power dissipation reduction of 18.46% when compared to conventional circuit topologies and is designed using fourteen transistor count, and contributes better performance with respect to power delay product values.