Fault Emulation in Digital Circuits using FPGA based Software-Hardware Co-Simulation

This paper presents a semi-automated framework for emulation of single stuck-at faults in combinational circuits. The proposed fault emulation framework is established with the help of software-hardware co-simulation employing an ARM-SoC and an FPGA. This work also gives an emphasis on devising a C++ based EDA tool which aids in an automatic generation of fault injectable module required for the purpose of fault emulation. The efficacy of the proposed framework is verified through fault emulation of ISCAS’85 benchmark circuits, namely, C17, C432, C1355 and C1908. The test patterns used for emulation are obtained from commonly known open source ATPG tool ‘ATALANTA’ and the fault emulation results for each Circuit under Test (CUT) are compared with that obtained using ‘HOPE’ simulator. As the complexity of the CUT increases in terms of number of gates, the number of faults to be emulated also increase. The proposed scheme facilitates the provision for applying as many test patterns as the test engineer wants. However, the emulation of faults runs serially. The proposed approach is able to detect the circuit nodes stuck-at high or low voltages through fault emulation. Fault emulation results show that the number of test patterns required for fault testing of C1908 is lesser than that of C1355. However, the number of modelled faults for C1908 is greater than that of C1355. Most importantly, the proposed fault emulation framework poses a merely negligible FPGA resource overhead while achieving a speed up in fault detection over traditional computer simulation techniques.