Impact of Area-to-Perimeter Ratio Layout Effect on TDDB in 45-nm PDSOI N-channel FETs

In this work, we present the effect of device layout and gate area-to-perimeter ratio on TDDB. DC and RF FETs in 45-nm RFSOI technology are subjected to gate stress at an elevated temperature of 125° C. TDDB characteristics, such as breakdown time, Weibull slope, voltage acceleration exponent, and safe operating voltage of devices are experimentally measured and analyzed. Non-Poisson area scaling is observed in RF FETs, however, DC FET measurements show a good correlation with the existing Poisson area scaling equation. Further, the effect of multiple gate fingers and device multiplicity on oxide degradation is studied. The power law voltage acceleration model is also analyzed and a 10 -year lifetime estimation based safe operating voltage is projected to be 1.7 V in RF FETs and 1.3 V in DC FETs.