Improved Process Induced Threshold Voltage Variability in Negative Capacitance Junctionless Transistors

Through well-calibrated simulations, this work reports on the process-induced threshold voltage $(V_{\text {th }})$ variability $\sigma(\Delta V_{\mathrm{th}})$ in junctionless (JL) and negative capacitance (NC) JL transistors. Results highlight that $\sigma(\Delta V_{\text {th }})$ against the statistical variation in structural parameters such as film $(T_{\mathrm{si}})$ and equivalent oxide (EOT) thicknesses, channel doping $(N_{\mathrm{ch}})$, and gate length $(L_{\mathrm{g}})$ is lower in NCJL transistors than its conventional counterparts. A systematic methodology showcases that $\sigma(\Delta V_{\text {th }})$, owing to the process variation, can be reduced by designing the NCJ devices with moderately doped channels $(N_{\mathrm{ch}} \sim 10^{18} \mathrm{~cm}^{-3})$. For fair assessment, the $\sigma(\Delta V_{\text {th }})$ of NCJL devices $(\text{@} N_{\mathrm{ch}} \sim 10^{18} \mathrm{~cm}^{-3})$ is compared with NC inversion mode (IM) transistors, and results highlight that $\sigma(\Delta V_{\text {th }})$ obtained in NCJ transistor is comparable with NCIM device. This work underscores the critical importance of designing NCJ devices with moderately doped channel while highlighting their potential significance in advanced semiconductor applications.