A Design of a Power Specific Processor Based on RISC-V Architecture

As the power network system continues to develop towards an increasingly complex scale, higher requirements are put forward for the implementation of power system relay protection algorithms. Fast Fourier transform (FFT), digital filter (FIR), as widely used algorithms in power systems, are the most core and complex algorithms in the field of digital signal processing (DSP), and the performance of FFT algorithms will affect the computing efficiency of the entire system. Application Specific Instruction Set Processor (ASIP) offers the advantages of customization, high performance, programmability and flexibility. In this paper, we will introduce an ASIP implementation based on RISC-V instruction set for power system relay protection applications, the processor implements the special operation instructions of FFT/IFFT, FIR and DFT algorithms customized for power application scenarios, in which FFT uses the mixed-based principle to achieve operation support from 24 points to 2048 points, and the measured data shows that there are great advantages in the number of supported points and efficiency.