A Calibrated Memristor Model Implementation for an SR-Latch Based on CMOS-Memristor Technology

An SR-Latch based on CMOS-memristor technol-ogy has been implemented in LT-spice, employing memristors calibrated with experimental data. Initially, we analyzed the electrical behavior of
$\text{HfO}_{2}$
-based ReRAMs to acquire key parameters essential for calibrating the memristor model. This calibration process generates the inherent variability reported for these devices. After, we build an OR gate with two calibrated memristors that, according to the analysis, work under the logical principles that govern the OR gate operation. Finally, the SR-Latch was implemented at the circuit level in LTspice. The outputs demonstrate that the latch exhibited a high accuracy, which implies that the memristor's variability does not affect the desired operation.