A brief Survey of Ultra-Low-Voltage CMOS: Approaching the Diffusion Limit

The minimum supply voltage for the standard inverter-based CMOS logic is 36 mV at room temperature. In this brief, we review some circuits that can operate from voltages below that limit. We show that the three-stacked inverter element can lower the minimum supply voltage to 30 mV. Also shown are some circuits that use positive feedback, and passive voltage gain for attaining a minimum supply voltage below the 36 mV limit. For each of the circuits presented, we focus on the design parameters that must be tuned to allow operation at the lowest supply voltage,