A 146pW, 0.4V, 0.015%/V Line Sensitivity, High PSRR Leakage-Biased CMOS Voltage Reference with the Optimization of Body Parasitic Effects

This paper presents a picowatt leakage-biased CMOS voltage reference (CVR) for application in ultra-low-power ultra-low-voltage consumer electronics. The proposed circuit maximally minimizes the interference of supply voltage (V
DD
) disturbance on the reference voltage
$(\mathbf{V}_{\mathbf{REF}})$
by optimizing body parasitic effects. To suppress the leakage current susceptible to
$\mathbf{v}_{\mathbf{DD}}$
caused by the parasitic bulk diode and noise in
$\mathbf{v}_{\mathbf{DD}}$
coupled through the parasitic capacitance between N-well and diffusion region, the body of PMOS as an active load is grounded. And the competitive line sensitivity (LS) and power supply rejection ratio (PSRR) can be obtained. With the proposed schemes, the design using a 0.18-µm CMOS process can generate an average reference voltage of 150 mV, while consuming only 146 pW with a minimum supply voltage of 0.4 V at room temperature. It achieves a LS of 0.015 %N from 0.4 V to 1.8 V. The PSRRs at 10 Hz, 100 Hz and 100 kHz are
$-96.0\text{dB}, -89\text{dB}$
and -62 dB, respectively. The average temperature coefficient is simulated as 13.06
$\mathbf{ppm}/^{\circ}\mathbf{C}$
from 0°C to 100°C and the active area is
$4752 \mu{\mathrm{m}}^{2}$
.