Performance Analysis of Low Power Hybrid Full Adder Using Pass Transistor Logic

Adders play an most vital role in the logical operations of VLSI circuits, with the fast increasing of the electronics technologies, speed and size of the system improved which is indirectly depends on the performance speed of the adder. In this proposed paper hybrid full adder is implemented by XNOR and AND logics with pass transistor logic (PTL) same as CMOS with less no of transistors that optimize the area, power, delay and increases the reliability of the circuit. Here the hybrid adder is implemented with 16 transistors and the performances of the parameters are more optimized, when we compare to the previous designs. It is performed in the various operating frequencies and temperature to calculate the power which is reduced up to 25% and delay, noise are optimized to 40% in this circuit. We calculated the parameters like power, delay, leakage current, and leakage voltage in the different temperatures and removed the knot in the simulation of the hybrid full adder. These total values are calculated with the DC voltage of 0.7 V and at 27°c temperature, with the decrease in the supply voltage or operating voltage there is the decrease in the delay and the noise. These total simulation works are done in cadence virtuoso tool in 45 nm technology.